Double-sided capacitor structure for a semiconductor device and a method for forming the structure

ABSTRACT

A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

This is a division of U.S. Ser. No. 10/150,622 filed May 17, 2002 andissued Sep. 14, 2004 as U.S. Pat. No. 6,790,725.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor manufacture and,more particularly, to a double-sided capacitor structure and a methodfor forming the structure.

BACKGROUND OF THE INVENTION

During the manufacture of semiconductor devices which comprise memoryelements, such as dynamic random access memories (DRAMs), static randomaccess memories (SRAMs), and some microprocessors, container capacitorsare commonly formed. Container capacitors are well known to allow anincreased stored charge over planar capacitors by increasing the surfacearea on which the charge can be stored. To further increase the surfacearea on which the charge can be stored, polysilicon storage nodes arecommonly converted to hemispherical silicon grain (HSG) polysilicon.This material has a roughened surface compared with non-HSG polysilicon,and therefore an increased surface area on which a charge can be stored.

FIGS. 1–8 depict a conventional method for forming a container capacitorfrom HSG polysilicon. FIG. 1 depicts a semiconductor wafer substrateassembly 10 comprising a semiconductor wafer 12 having a plurality ofdoped areas 14 which allow proper operation of a plurality oftransistors 16. Each transistor comprises gate oxide 18, a dopedpolysilicon control gate 20, silicide 22 such as tungsten silicide toincrease conductivity of the control gate, and a capping layer 24 oftetraethyl orthosilicate (TEOS) oxide. Silicon nitride spacers 26insulate the control gate 20 and silicide 22 from polysilicon pads 28 towhich the container capacitors will be electrically coupled. Furtherdepicted in FIG. 1 is shallow trench isolation (STI, field oxide) 30which reduces unwanted electrical interaction between adjacent controlgates, and a thick layer of deposited oxide 32 such asborophosphosilicate glass (BPSG). A patterned photoresist layer 34defines the location of the container capacitors to be formed. The FIG.1 structure may further include one or more bit (digit) lines under theTEOS layer or various other structural elements or differences which,for simplicity of explanation, have not been depicted.

The FIG. 1 structure is subjected to an anisotropic etch which removesthe exposed portions of the BPSG layer to form a patterned BPSG layerwhich provides a base dielectric having a recess for the containercapacitor. During this etch the polysilicon pads 28 and possibly aportion of TEOS capping layer 24 are exposed as depicted in FIG. 2. Theremaining photoresist layer is stripped and any polymer (not depicted)which forms during the etch is removed according to means known in theart to provide the FIG. 3 structure.

As depicted in FIG. 4, a blanket polysilicon layer 40 is formedconformal with the deposited oxide layer, and will provide a containercapacitor storage node for the completed capacitor. A thick blanketfiller material 42, such as photoresist, is formed to fill thecontainers provided by polysilicon 40. The FIG. 4 structure is thensubjected to a planarizing process, such as a chemical planarization, amechanical planarization, or a chemical mechanical planarization (CMP)step. This process removes horizontal portions of the photoresist 42,the polysilicon 40, and likely a portion of the BPSG 32 to result in theFIG. 5 structure.

Next, the BPSG 32 is partially etched with an etch selective topolysilicon (i.e. an etch which minimally etches or, preferably, doesn'tetch polysilicon) to result in the structure of FIG. 6. At this point inthe process the polysilicon storage nodes 40 are only minimallysupported. The bottom plates 40 in the FIG. 6 structure each comprise afirst region 60 which defines a recess, and a second region 62 whichdefines an opening to the recess, with the first and second regionsbeing continuous, each with the other. In other words, the bottom plate40 of FIG. 6 defines a receptacle having a rim 62 which defines anopening to the interior of the receptacle. The regions 60, 62 formvertically-oriented sides of the bottom plate, and the sides areelectrically-coupled by a horizontally-oriented bottom 64.

After etching the BPSG, a process is performed which converts the smoothpolysilicon to HSG polysilicon storage plates 70 as depicted in FIG. 7.Various processes for converting the smooth polysilicon to HSGpolysilicon are known in the art.

After performing the conversion of the smooth polysilicon to HSGpolysilicon, a cell dielectric layer 80, for example a layer ofhigh-quality cell nitride, a polysilicon container capacitor top plate82, and a planar oxide layer such as BPSG 84 are formed according tomeans known in the art to result in the FIG. 8 structure. Subsequently,wafer processing continues according to means known in the art.

One problem which can result during the process described above isflaking of the HSG polysilicon from the storage node 70 as depicted inFIG. 9. These loose portions 90 are conductive and thus, when they breakoff and contact two adjacent conductive structures, can short thestructures together and result in a malfunctioning or nonfunctioningdevice. Typically, the greatest number of such defect occurs at the topof the storage plates. This may occur as these ends are not protected byadjacent structures. This may also occur because as wafer processingcontinues the tops are the most likely portion of the storage plate tobe contacted during a CMP or other step, and also incur the higheststresses.

Another problem which can occur with the process described above resultsfrom the very close lateral spacing between adjacent storage plates. Asa design goal of semiconductor engineers is to form as many storagecapacitors per unit area as possible, and there are typically severalmillion storage capacitors on each memory chip, even a small decrease inspacing between features can allow for the formation of many morefeatures in the same area. Thus the capacitors are formed as closetogether as wafer processing will allow. As the roughened polysilicongrains grow, grains from two adjacent plates can form a bridge 92between the two plates and thus short them together to result in amalfunctioning device.

Forming the capacitor structures close together such that there is verylittle space between adjacent double-sided containers also makes itlikely that particles of contamination will be trapped between adjacentcontainers to result in shorting between the containers. Given thenormally tight and deep spaces of the structure, it is difficult orimpossible to reliably remove the particles which contaminate the wafersurface with conventional cleaning steps currently available in thefield of semiconductor device manufacturing.

A method used to form container capacitor storage plates which reducesor eliminates the problems described above, and a structure resultingtherefrom, would be desirable.

SUMMARY OF THE INVENTION

The present invention provides a new method which, among otheradvantages, reduces problems associated with the manufacture ofsemiconductor devices, particularly problems resulting during theformation of double-sided capacitor structures (i.e. capacitorstructures having the capacitor top plate formed on two sides of thebottom plate, the inside and the outside of the container, as depictedin FIG. 8). In accordance with one embodiment of the invention anopening is provided in an oxide layer and a first continuous polysiliconlayer is formed within the opening. The first polysilicon layer isplanarized, for example using a mechanical or chemical mechanicalpolishing (CMP) process. The first polysilicon layer, which will form aportion of the capacitor top plate, is then etched to form a pluralityof recesses therein.

After forming the plurality of recesses in the first polysilicon layer,a blanket cell dielectric layer and a blanket second polysilicon layerare formed within the recesses. The second polysilicon and the celldielectric are cleared from horizontal surfaces, including the uppersurface of the first polysilicon layer. As the second polysilicon layerprovides a seed layer for a roughened or textured layer such as ahemispherical silicon grain (HSG) polysilicon layer, the secondpolysilicon layer is converted to HSG polysilicon. Subsequently, theupper surface of the structure is planarized to remove the polysiliconfrom the surface, then the first and second polysilicon layers arerecessed within the oxide using an etch selective to oxide (i.e. an etchwhich minimally etches or, preferably, does not etch oxide duringetching of the polysilicon). A second cell dielectric layer is formed,and a third polysilicon layer is provided over the second celldielectric layer, and within the recess formed in the plurality ofrecesses in the first polysilicon layer, which will form a secondcapacitor top plate layer.

After forming the second top plate layer, the first and second top platelayers are electrically coupled. Wafer processing continues according tomeans known in the art.

Using this process the highest defect source for HSG flaking is removedas a flaking source, which results in decreased device defects. Variousembodiments of the inventive method, and an inventive structureresulting from the method, are described.

Advantages will become apparent to those skilled in the art from thefollowing detailed description read in conjunction with the appendedclaims and the drawings attached hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1–8 are cross sections depicting a conventional process forforming a container capacitor;

FIG. 9 is a cross section depicting two possible failure modes which mayoccur during the conventional process of FIGS. 1–8;

FIG. 10 is a cross-sectional isometric view depicting an array ofcontainer capacitor storage plates prior to formation of cell dielectricand the capacitor top plate;

FIGS. 11–22 are cross sections depicting intermediate structuresobtained during an embodiment of the present invention;

FIG. 23 is a cross section detailing a portion of the FIG. 21 structure;

FIGS. 24 and 25 are cross sections detailing portions of the FIG. 22structure;

FIGS. 26–28 are cross sections depicting intermediate structuresobtained during an embodiment of the present invention;

FIG. 29 is a plan view depicting an intermediate structure obtainedduring an embodiment of the invention; and

FIG. 30 is a cross section depicting an intermediate structure obtainedduring an embodiment of the invention of FIG. 29.

It should be emphasized that the drawings herein may not be to exactscale and are schematic representations. The drawings are not intendedto portray the specific parameters, materials, particular uses, or thestructural details of the invention, which can be determined by one ofskill in the art by examination of the information herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A first embodiment of an inventive method for forming a containercapacitor structure is depicted in FIGS. 11–25.

FIG. 11 depicts a semiconductor structure having elements in common tothose of FIG. 1 including a semiconductor wafer 12, source/drain regions14, transistors 16, and shallow trench isolation 30. FIG. 11 furtherdepicts a region within a container capacitor array 110, and a region ina periphery 112 of the device. While four transistors 16 are depicted inthe array 110, it is likely that several thousand transistors, and morelikely that several million transistors, will be located in the array.The periphery 112 comprises a diffusion region 114 to which a conductivepad 115 is electrically coupled, formed at the same time as pads 28. Itshould be noted that simultaneous processing on the array and on theperiphery of the device is described herein to demonstrate that suchsimultaneous processing is possible. The inventive processing may alsobe carried out on only the array of the device, while processing in theperiphery is performed separately.

FIG. 11 further depicts an optional etch stop layer 116 such as asilicon nitride layer between about 50 angstroms (Å) and about 1,000 Åthick, a deposited and planarized dielectric layer 118 such as a layerof borophosphosilicate glass (BPSG) between about 5,000 Å and about50,000 Å thick, and a patterned photoresist layer 120. The patternedphotoresist layer exposes dielectric 118 in the region of the array inwhich container capacitors will be formed. The width of the exposedportion of the dielectric can extend the entire length and width of theentire array, or the photoresist can expose the array using a pluralityof openings, with each opening exposing a portion of the array. In mostuses of the invention, however, the entire area of the wafer substrateassembly which will eventually comprise memory container capacitors willbe exposed by the photoresist layer whether through one or more than oneopening in the photoresist.

Next, as depicted in FIG. 12, the dielectric layer 118 is only partiallyetched through its thickness to form a well 122 within the dielectric118. Generally, between about half to about three-quarters of thedielectric layer thickness will be etched. Further, the depth of theetch is proportional to the capacitance of the completed capacitor, butthe underlying layers should not, in most embodiments, be exposed atthis point in the process.

After the dielectric 118 is etched to result in well 122, thephotoresist 120 is removed and a blanket first capacitor top plate layer130 is formed over the wafer surface as depicted in FIG. 13. Thepreferred first top plate material is polysilicon, and is referred to assuch throughout this document, however other materials may also functionsufficiently with modifications, such as different etches, which will beapparent to one of skill in the art from the information herein. Thethickness of the polysilicon 130 is equal to or thicker than the depthof the well entirely filling the well. Any excess polysilicon whichoverfills the well will be removed in subsequent processing. Aconductive layer of conductively-doped polycrystalline silicon 130between about 5,000 Å and about 80,000 Å may be formed using plasmaenhanced chemical vapor deposition (PECVD) techniques. For example,silane gas (SiH₄) is introduced as a silicon source into a depositionchamber at a flow rate of between about 400 standard cubic centimeters(sccm) and about 600 sccm along with phosphine (PH₃) at a flow rate ofbetween about 5 sccm and about 15 sccm at a temperature of between about500° C. and about 600° C. Using this process the preferred material isformed at a rate of between about 10 Å/min to about 20 Å/min, so for thewell between about 5,000 Å and about 50,000 Å, a polysilicon processingduration of between about 8.3 hours and about 83.3 hours is required toform a conductively-doped layer.

After forming the structure of FIG. 13, at least the capacitor top platelayer 130 is planarized to result in a substantially planar top platelayer 130 as depicted in FIG. 14. Layer 130 can be planarized usingmechanical polishing or chemical mechanical polishing (CMP). Further, aportion of the dielectric 118 may also be removed during polishing oflayer 130, for example if layer 130 has been formed to less thancompletely fill the well 122. The polishing results in removal of thecapacitor top plate layer 130 from the upper surface of the dielectric118, and preferably results in the first top plate layer remaining 130remaining only in the well.

After forming and planarizing layer 130, a patterned photoresist layer140 is formed over the top plate layer 130 and dielectric 118 asdepicted in FIG. 14. Openings in the resist 140 expose locations of thetop plate layer 130 and dielectric 118 which are to be etched, forexample the portions overlying contact pads 28.

Next, the exposed portions of top plate layer 130 and dielectric 118 areetched down to the level of the etch stop layer 116. An anisotropic etchwhich removes only polysilicon can be used to etch layer 130 to exposelayer 118 under top plate layer 130, then once dielectric 118 is exposeda second etch can be used to remove layer 118 in the array 110 and inthe periphery 112 down to the level of etch stop 116. An etch whichremoves polysilicon selective to dielectric such as BPSG (i.e. removespolysilicon with little or no etching of the dielectric 118) includesexposing the polysilicon to Cl₂ and CF₄ in a 3:1 ratio at a pressure ofabout 10 millitorr and at a power of about 300 watts in a high-densitytool. The etch can also be performed in a reactive ion etcher (RIE) toolat a pressure of about 100 millitorr and a power of about 300 wattsusing Cl₂ and HBr in a 1:3 ratio. After the thickness of the first topplate layer is removed to expose dielectric 118 which forms the bottomof well 122, etching stops due to the low or nonexistent etch rate ofdielectric 118 during the etch of the first top plate layer. Afteretching the first top plate layer 130 it will typically comprise acontinuous layer having a plurality of round or oval openings therein,or possible openings of another shape, when viewed from above. This etchforms cross-sectional sidewalls in polysilicon 130 which define theopenings therein. After etching the openings in layer 130, ananisotropic dielectric etch is performed which removes layer 118selective to the etch stop layer 116 to result in the FIG. 15 structure.An anisotropic etch which removes the dielectric of layer 118, forexample BPSG, selective to the etch stop layer, for example to stop onsilicon nitride (Si₃N₄), includes the use of C₄F₈, argon, and O₂ at apressure of about 30 millitorr and a power of 1500 watts in a reactiveion etcher. In the alternative to using the two etches as describedabove, one for the first top layer 130 and a second for dielectric layer118, a single anisotropic etch can be performed which removes layer 130and layer 118 selective to layer 116.

Etch stop layer 116 therefore allows etching of materials with differentetch rates (the first top plate layer 130 and dielectric layer 118), ordifferent thicknesses, without over etching an underlying layer. Analternative would be to omit the formation of etch stop layer 116, thenetch layer 130 with an etch which removes polysilicon 130 selective todielectric 118. Subsequently, after removing the thickness of layer 130to expose layer 118 underneath, an etch is performed which removesdielectric 118 selective to the material of layer 28 and 115. This wouldrequire an etch which is highly selective to prevent etching of layers28 and 115 during an extended etch of dielectric 118 to expose pad 115.

After forming the FIG. 15 structure the etch stop layer is etched toexpose pads 28 and 115 as depicted in FIG. 16. An anisotropic etch of asilicon nitride etch stop layer may comprise an etch using CF₄ or CHF₃and argon at a pressure of about 30 millitorr and a power of about 350watts. This etches the Si₃N₄ with little or no etching of the pads 28and 115, and results in the structure of FIG. 16.

After forming the FIG. 16 structure a first layer of cell dielectric 170and a capacitor bottom plate seed layer 172 are formed as depicted inFIG. 17. A cell dielectric layer 170, such as cell nitride, can beformed according to means known in the art. A polysilicon bottom plateseed layer 172 having a target thickness of between about 50 Å and about150 Å may be formed using plasma enhanced chemical vapor deposition(PECVD) techniques. For example, silane gas (SiH₄) is introduced as asilicon source into a deposition chamber at a flow rate of between about400 sccm and about 600 sccm along with phosphine (PH₃) at a flow rate ofbetween about 5 sccm and about 15 sccm at a temperature of between about500° C. and about 600° C. for a duration of between about 2.5 minutesand about 15 minutes. Using this process the preferred material isformed at a rate of between about 10 Å/min to about 20 Å/min. As thelayer forms the PH₃ flow rate may be decreased to 0 sccm over a periodof about 10 seconds as the layer approaches about half its finalthickness. This forms a layer 172 of between about 50 Å and about 150 Åthick.

Next, the first cell dielectric layer 170 and bottom plate seed layer172 are removed from horizontal surfaces of the FIG. 17 structure usinga spacer etch which etches the seed layer at a slower rate than itetches the dielectric to result in the etched nitride 170 andpolysilicon as depicted in FIG. 18. A spacer etch is also known to etchhorizontal surfaces at a faster rate than vertical surfaces. This etchforms spacer structures from the bottom plate seed layer 172, and maypartially etch the first top plate layer 130. FIG. 18 further depicts aplanar photoresist layer 180 formed after the spacer etch. A CMP step isperformed on the FIG. 18 structure to result in the structure of FIG. 19which has a planar upper surface.

Next, the FIG. 19 structure is exposed to a bath of hydrofluoric acid(HF) then a bath of tetramethyl ammonium hydroxide (TMAH). Exposure toHF and TMAH provides a post-CMP clean and further results in recessingof polysilicon 130, 172, and the photoresist 180. The nitride, however,remains unetched by the HF and TMAH thereby forming the FIG. 20structure. A subsequent photoresist clean, for example an ash step thena wet clean in a solution of sulfuric acid (H₂SO₄) and hydrogen peroxide(H₂O₂), removes the photoresist 180 to result in the FIG. 21 structure.

After forming the FIG. 21 structure the polysilicon bottom plate seedlayer 172 may, optionally, be converted to hemispherical silicon grain(HSG) polysilicon 220 as depicted in FIG. 22. This step may be performedusing disilane gas (Si₂H₆) in a CVD system. The disilane gas isdecomposed into silicon radicals, then nucleation is performed and thesmooth polysilicon is converted to HSG silicon. After converting theseed layer to HSG 220, a second cell dielectric layer 222 is formed overexposed surfaces according to means known in the art.

Prior to converting the bottom plate seed layer to HSG polysilicon theseed layer may not actually contact pads 28, 115. FIG. 23 depicts detailof the FIG. 21 structure comprising pad 28, first cell dielectric layer170 and seed layer 172. After converting the seed layer to HSGpolysilicon, however, seed layer 172 expands to contact 28 and makeelectrical contact therewith as depicted in FIG. 24. Depending on thedoping, pad 28 may also have some slight conversion to HSG during theconversion of the seed layer to HSG 220 as depicted in FIG. 24.

FIG. 25 depicts detail of the upper surface of the FIG. 22 structure. Asa wet etch of the bottom plate layer with HF and TMAH as described aboveremoves dielectric at a slower rate than it etches polysilicon, an upperportion of the first cell dielectric layer 170 extends above an upperportion of the bottom plate layer 220 and above an upper portion offirst top plate layer 130 which is etched after removal of thehorizontal portions of the first cell dielectric layer 170 during theetch between FIG. 17 and FIG. 18. If the upper portions of the firstcell dielectric layer 170, bottom plate layer 220, and first top platelayer 130 were at the same level, polysilicon layers 220 and 130,portions of the bottom capacitor plate and top plate respectively, wouldbe separated only by the thickness of the first cell dielectric layer170. Forming a protruding second cell dielectric layer 222 as depicted“seals” the bottom plate layer 220 and electrically isolates it duringoperation of the completed device from the first top plate layer 130.Thus leakage of a charge stored on a capacitor comprising the first topplate layer 130 and bottom plate 220 is more resistant to charge leakagebetween layers 130 and 220 than if the protruding portion of the nitride170 was not formed.

Referring to FIG. 26, after converting bottom plate 220 to HSG andforming the second cell dielectric layer 222, a patterned secondcapacitor top plate layer 260, for example a polysilicon layer betweenabout 150 Å and about 5,000 Å thick, is formed according to means knownin the art. Layer 260 is formed over the majority of the array, and inthis embodiment is not formed over a portion of at least one first topplate layer portions. As depicted in FIG. 26 the first 130 and second260 capacitor top plate layers in this embodiment are not yetelectrically connected. However, various process modifications may allowfor their coupling upon formation of layer 260. The present methoddescribes various additional steps to electrically connect the twolayers as described below. Further, FIG. 26 depicts a conductive plug262 formed in the periphery concurrently during formation of thecapacitor structures in the array, and is formed from layer 260.Formation of plug 262 is not required for the practice of the invention,but is depicted to demonstrate that concurrent processing of containercapacitors in the array and conductive plugs in the periphery ispossible and may be preferred to minimize mask steps.

In the present embodiment, subsequent to forming the FIG. 26 structure,a planar dielectric layer 270 and a patterned photoresist layer 272 areformed as depicted in FIG. 27 according to means known in the art. Thephotoresist layer exposes the dielectric layer 270 at opening 274 and atopening 276. Opening 274 in this embodiment overlies at least a portionof the first container capacitor top plate layer 130, the portion whichremains uncovered in FIG. 23. Opening 276 overlies a diffusion region278, and this depiction demonstrates that another conductive feature,for example a digit (bit) line contact plug, may be formed concurrentlyduring the capacitor formation to minimize mask steps. After formingdielectric 270 and photoresist 272, the exposed structures are etched toexpose diffusion region 278 and to etch a portion of the exposed topplate layer 130.

A sufficient etch which removes the exposed dielectric comprises the useof CF₄ at a flow rate of 10 sccm, O₂ at a flow rate of 8 sccm, either ofC₄F₆ or C₄F₈ at a flow rate of about 28 sccm, and argon at a flow rateof about 400 sccm using a power of between about 1400 watts and about1900 watts, a pressure of about 35 millitorr for a duration of betweenabout 60 seconds and about 140 seconds. This anisotropic etch clears thedielectric 270, 222, 118 from over diffusion region 278, and etchesdielectric layers 270, 222, 118 over and around the first top platelayer portion 130 exposed in FIG. 23. During this etch a polymer 280forms to coat exposed surfaces in the area where polysilicon is beingetched, and eventually functions as an etch stop layer to preventfurther etching of the polysilicon and dielectric in this region. Thisetch, therefore, is self-limiting in this area and prevents over etchingof the polysilicon first top plate layer 130.

In another embodiment of the invention layer 260 in FIG. 26 is formed tocover all first top plate layer portions 130. A first etch then removesdielectric 260, polysilicon 260 which covers layer 130, and possiblycell dielectric 222. Subsequently, a second etch, which forms polymer280, is used to etch layer 130 and possibly cell dielectric 222. Thistwo-step etch is required to prevent polymer buildup during the etch oflayer 260 which would stop etching before layer 260 is etched completelythrough. A second alternative would be to alternate the polymer-formingetch of layer 260 with a polymer-clearing etch to remove the polymeruntil layer 260 is etched completely through. After layer 260 is etchedthrough, the polymer-forming etch may be continuously applied thereafterto form the structure of FIG. 27.

Subsequent to forming the FIG. 27 structure the polymer is cleared, forexample using a dry strip using O₂ then a wet etch in a bath of H₂SO₄. Ablanket conductive layer is formed over the wafer surface and within theopenings at 274 and 276, and is then planarized to result in the FIG. 28structure. Conductive strap 282 electrically connects first top platelayer 130 with second top plate layer 260, and conductive plug 284provides an electrical connection of diffusion region 278. As layer 130is a continuous layer as depicted in the plan view of FIG. 29, strappinglayer 130 to layer 260 in a single location as depicted in FIG. 28electrically connects all portions of layer 130 with layer 260. However,a single connection point may have an excessive resistance, and thus aplurality of connections points will be preferred in most embodiments.

FIG. 29 depicts a plan view of a structure similar to that of FIG. 28,except that FIG. 29 depicts a plurality of “tabs” 290, which allow foran expanded point at which to connect the first 130 and second 260 topplate layers. FIG. 30 depicts a cross section of the FIG. 29 structurealong A—A. Using the tabs as depicted, a dielectric etch which isselective to polysilicon may be used for the entire etch if layer 260 ispatterned so that layer 260 is formed to have an opening over layer 130.If polysilicon 260 is formed over layer 130, an etch which removes bothdielectric and polysilicon may be used to etch through polysilicon 260and, once layer 260 is etched through, a dielectric etch selective topolysilicon may be continued until layer 130 is exposed. Plug 282 isformed in accordance with the description relative to FIG. 28 toelectrically connect layer 260 with tabs 290 which are portions of firstcontainer capacitor top plate layer 130.

In another embodiment the polysilicon seed layer 172 of FIG. 17 may beconverted prior to forming photoresist layer 180 of FIG. 18. HSGconversion in this embodiment may be completed before the anisotropicetch which removes the seed layer from layer 28, or preferably after theanisotropic etch.

It is contemplated that semiconductor device comprising the inventionmay be attached along with other devices to a printed circuit board, forexample to a computer motherboard or as a part of a memory module usedin a personal computer, a minicomputer, or a mainframe. The inventivedevice may further be useful in other electronic devices related totelecommunications, the automobile industry, semiconductor test andmanufacturing equipment, consumer electronics, or virtually any piece ofconsumer or industrial electronic equipment.

While this invention has been described with reference to illustrativeembodiments, this description is not meant to be construed in a limitingsense. Various modifications of the illustrative embodiments, as well asadditional embodiments of the invention, will be apparent to personsskilled in the art upon reference to this description. It is thereforecontemplated that the appended claims will cover any such modificationsor embodiments as fall within the true scope of the invention.

1. A semiconductor device comprising: a first conductive capacitor topplate layer having a plurality of openings therethrough; a plurality ofconductive capacitor bottom plates with one bottom plate formed at leastpartially within each opening in the first conductive capacitor topplate layer, wherein each bottom plate is separated from the firstcapacitor top plate layer by a first cell dielectric layer, and eachbottom plate having an opening therein which defines a receptacle; asecond conductive capacitor top plate layer formed within the receptacledefined by each of the plurality of capacitor bottom plates andelectrically coupled with the first conductive capacitor top platelayer, wherein the second conductive capacitor top plate layer isseparated from each capacitor bottom plate by a second cell dielectriclayer.
 2. The semiconductor device of claim 1 further comprising aplurality of contact pads, wherein each contact pad is electricallyconnected to one of the conductive capacitor bottom plates.
 3. Thesemiconductor device of claim 2 further comprising the second celldielectric layer contacting each contact pad.
 4. The semiconductordevice of claim 1 further comprising a conductive strap which contactsboth the first and second conductive capacitor top plate layers toelectrically connect the first and second conductive capacitor topplates together.
 5. The semiconductor device of claim 1 wherein a heightof the second conductive capacitor top plate layer is greater than aheight of the first conductive capacitor top plate layer.
 6. Thesemiconductor device of claim 1 further comprising an upper portion ofthe first cell dielectric layer extending above an upper surface of thefirst conductive capacitor top plate layer and of an upper surface ofeach conductive capacitor bottom plate.
 7. The semiconductor device ofclaim 6 further comprising the second cell dielectric layer contactingthe first cell dielectric layer at the upper portion of the first celldielectric layer.
 8. The semiconductor device of claim 1 wherein thebottom plate is a hemispherical silicon grain (HSG) layer.
 9. Asemiconductor device comprising: a storage capacitor comprising: a firstcapacitor top plate layer having a plurality of openings therethrough; aplurality of capacitor bottom plates, with each bottom plate located atleast partially within one of the plurality of openings in the firstcapacitor top plate layer, wherein each bottom plate comprises a recesstherein; a second capacitor top plate layer partially located withineach of the plurality of openings in the first capacitor top plate layerand within each recess of each bottom plate and having a portion locatedover each capacitor bottom plate and a portion located over the firstcapacitor top plate layer; and a conductive strap which contacts boththe first and second capacitor top plate layers.
 10. The semiconductordevice of claim 9 further comprising: a first cell dielectric layerwhich separates the first top plate layer from each bottom plate; and asecond cell dielectric layer which separates each bottom plate from thesecond capacitor top plate layer and which separates the first capacitortop plate layer from the second capacitor top plate layer.
 11. Thesemiconductor device of claim 10 further comprising the conductive strapcontacting the second cell dielectric layer.
 12. The semiconductordevice of claim 9 wherein the bottom plate is a hemispherical silicongrain (HSG) layer.